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Leszy

Leszy [lɛʂɨ] is a superscalar out-of-order RISC-V written in VHDL. It is developed in the Computer Engineering group at the Osnabrück University.

Quick-start

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Features

The Leszy design focuses on the following key features:

Performance : As a superscalar out-of-order core, performance has to be one focus points for the design. Leszy is intended as a general purpose core and there as one of the main compute units of a SoC, providing significant processing power.

Configurability : Many aspects of the design can be parameterized, activated or deactivated entirely. This enables a large number of configurations, each adapted to a specific use case.

Vendor independence : Although the design was tested on Xilinx FPGAs during the development process, it is vendor-independent. This means that no vendor-dependent code blocks were used.

Reconfigurability : The most unique feature of Leszy will be the reconfigurability. This will allow Leszy to reconfigure itself on the fly during runtime. Utilizing the reconfigurability of FPGAs this enables the core to adapt its pipeline to the currently executed program. While this feature has not yet been implemented, the design was developed with this feature in mind. More information on the reconfigurability of Leszy will follow when it has been implemented.

!!! warning Although Leszy has already been successfully synthesised onto an FPGA, and it has successfully executed code, it is still at a very early stage of development. This means that errors can still occur, crucial features are missing, and the core has not yet reached its full potential.

Additional Information